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altera corporation 1 flex 8000 programmable logic device family september 1998, ver. 9.11 data sheet a-ds-f8000-09.11 flex 8000 3 features... n low-cost, high-density, register-rich cmos programmable logic device (pld) family (see table 1 ) 2,500 to 16,000 usable gates 282 to 1,500 registers n system-level features in-circuit reconfigurability (icr) via external configuration eprom or intelligent controller fully compliant with the peripheral component interconnect (pci) standard built-in joint-test action group (jtag) boundary-scan test (bst) circuitry compliant with ieee std. 1149.1-1990 on selected devices multivolt i/o interface enabling device core to run at 5.0 v, while i/o pins are compatible with 5.0-v and 3.3-v logic levels low power consumption (typical specification less than 0.5 ma in standby mode) n flexible interconnect fasttrack interconnect continuous routing structure for fast, predictable interconnect delays dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) tri-state emulation that implements internal tri-state nets n powerful i/o pins programmable output slew-rate control reduces switching noise n peripheral register for fast setup and clock-to-output delay table 1. flex 8000 device features feature epf8282a epf8282av epf8452a epf8636a EPF8820A epf81188a epf81500a usable gates 2,500 4,000 6,000 8,000 12,000 16,000 flipflops 282 452 636 820 1,188 1,500 logic array blocks (labs) 26 42 63 84 126 162 logic elements (les) 208 336 504 672 1,008 1,296 maximum user i/o pins 78 120 136 152 184 208 jtag bst circuitry yes no yes yes no yes
2 altera corporation flex 8000 programmable logic device family data sheet ...and more features n fabricated on an advanced sram process n available in a variety of packages with 84 to 304 pins (see table 2 ) n software design support and automatic place-and-route provided by the altera max+plus ii development system for 486- and pentium-based pcs, and sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations n additional design entry and simulation support provided by edif 2 0 0 and 3 0 0 netlist files, library of parameterized modules (lpm), verilog hdl, vhdl, and other interfaces to popular eda tools from manufacturers such as cadence, exemplar logic, mentor graphics, orcad, synopsys, synplicity, and veribest note: (1) flex 8000 device package types include plastic j-lead chip carrier (plcc), thin quad flat pack (tqfp), plastic quad flat pack (pqfp), power quad flat pack (rqfp), ball-grid array (bga), and pin-grid array (pga) packages. general description altera? flexible logic element matrix (flex ) family combines the benefits of both erasable programmable logic devices (eplds) and field- programmable gate arrays (fpgas). the flex 8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of fpgas with the high speed and predictable interconnect delays of eplds. logic is implemented in les that include compact 4-input look-up tables (luts) and programmable registers. high performance is provided by a fast, continuous network of routing resources. table 2. flex 8000 package options & i/o pin count note (1) device 84-pin plcc 100- pin tqfp 144- pin tqfp 160- pin pqfp 160- pin pga 192- pin pga 208- pin pqfp 225- pin bga 232- pin pga 240- pin pqfp 280- pin pga 304- pin rqfp epf8282a 68 78 epf8282av 78 epf8452a 68 68 120 120 epf8636a 68 118 136 136 EPF8820A 112 120 152 152 152 epf81188a 148 184 184 epf81500a 181 208 208
altera corporation 3 flex 8000 programmable logic device family data sheet flex 8000 3 flex 8000 devices provide a large number of storage elements for applications such as digital signal processing (dsp), wide-data-path manipulation, and data transformation. these devices are an excellent choice for bus interfaces, ttl integration, coprocessor functions, and high-speed controllers. the high-pin-count packages can integrate multiple 32-bit buses into a single device. table 3 shows flex 8000 performance and le requirements for typical applications. all flex 8000 device packages provide four dedicated inputs for synchronous control signals with large fan-outs. each i/o pin has an associated register on the periphery of the device. as outputs, these registers provide fast clock-to-output times; as inputs, they offer quick setup times. the logic and interconnections in the flex 8000 architecture are configured with cmos sram elements. flex 8000 devices are configured at system power-up with data stored in an industry-standard parallel eprom or an altera serial configuration eprom device, or with data provided by a system controller. altera offers the epc1, epc1213, epc1064, and epc1441 configuration eproms, which configure flex 8000 devices via a serial data stream. configuration data can also be stored in an industry-standard 32 k 8 bit or larger eprom, or downloaded from system ram. after a flex 8000 device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. because reconfiguration requires less than 100 ms, real- time changes can be made during system operation. f for information on how to configure flex 8000 devices, go to the following documents: n configuration eproms for flex devices data sheet n bitblaster serial download cable data sheet n byteblaster parallel port download cable data sheet n application note 33 (configuring flex 8000 devices) n application note 38 (configuring multiple flex 8000 devices) table 3. flex 8000 performance application les used a-2 speed grade a-3 speed grade a-4 speed grade units 16-bit loadable counter 16 125 95 83 mhz 16-bit up/down counter 16 125 95 83 mhz 24-bit accumulator 24 87 67 58 mhz 16-bit address decode 4 4.2 4.9 6.3 ns 16-to-1 multiplexer 10 6.6 7.9 9.5 ns
4 altera corporation flex 8000 programmable logic device family data sheet flex 8000 devices contain an optimized microprocessor interface that permits the microprocessor to configure flex 8000 devices serially, in parallel, synchronously, or asynchronously. the interface also enables the microprocessor to treat a flex 8000 device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to create configuration software. the flex 8000 family is supported by altera? max+plus ii development system, a single, integrated package that offers schematic, text?ncluding the altera hardware description language (ahdl), vhdl, and verilog hdl?nd waveform design entry; compilation and logic synthesis; simulation and timing analysis; and device programming. the max+plus ii software provides edif 2 0 0 and 3 0 0, library of parameterized modules (lpm), vhdl, verilog hdl, and other interfaces for additional design entry and simulation support from other industry- standard pc- and unix workstation-based eda tools. the max+plus ii software runs on 486- and pentium-based pcs, and sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations. the max+plus ii software interfaces easily with common gate array eda tools for synthesis and simulation. for example, the max+plus ii software can generate verilog hdl files for simulation with tools such as cadence verilog-xl. additionally, the max+plus ii software contains eda libraries that use device-specific features such as carry chains, which are used for fast counter and arithmetic functions. for instance, the synopsys design compiler library supplied with the max+plus ii development system includes designware functions that are optimized for the flex 8000 architecture. f for more information on the max+plus ii software, go to the max+plus ii programmable logic development system & software data sheet in this data book. functional description the flex 8000 architecture incorporates a large matrix of compact building blocks called logic elements (les). each le contains a 4-input lut that provides combinatorial logic capability and a programmable register that offers sequential logic capability. the fine-grained structure of the le provides highly efficient logic implementation. eight les are grouped together to form a logic array block (lab). each flex 8000 lab is an independent structure with common inputs, interconnections, and control signals. the lab architecture provides a coarse-grained structure for high device performance and easy routing.
altera corporation 5 flex 8000 programmable logic device family data sheet flex 8000 3 figure 1 shows a block diagram of the flex 8000 architecture. each group of eight les is combined into an lab; labs are arranged into rows and columns. the i/o pins are supported by i/o elements (ioes) located at the ends of rows and columns. each ioe contains a bidirectional i/o buffer and a flipflop that can be used as either an input or output register. figure 1. flex 8000 device block diagram signal interconnections within flex 8000 devices and between device pins are provided by the fasttrack interconnect, a series of fast, continuous channels that run the entire length and width of the device. ioes are located at the end of each row (horizontal) and column (vertical) fasttrack interconnect path. ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe i/o element (ioe) logic array block (lab) logic element (le) fasttrack interconnect
6 altera corporation flex 8000 programmable logic device family data sheet logic array block a logic array block (lab) consists of eight les, their associated carry and cascade chains, lab control signals, and the lab local interconnect. the lab provides the coarse-grained structure of the flex 8000 architecture. this structure enables flex 8000 devices to provide efficient routing, high device utilization, and high performance. figure 2 shows a block diagram of the flex 8000 lab. figure 2. flex 8000 logic array block carry-in and cascade-in from lab on left dedicated inputs le1 4 le8 4 4 le2 4 4 4 2 2 le3 4 le4 4 le5 4 le6 4 le7 4 column interconnect row interconnect 8 24 lab local interconnect (32 channels) 8 column-to-row interconnect carry-out and cascade-out to lab on right 8 16 lab control signals see figure 8 for details.
altera corporation 7 flex 8000 programmable logic device family data sheet flex 8000 3 each lab provides four control signals that can be used in all eight les. two of these signals can be used as clocks, and the other two for clear/preset control. the lab control signals can be driven directly from a dedicated input pin, an i/o pin, or any internal signal via the lab local interconnect. the dedicated inputs are typically used for global clock, clear, or preset signals because they provide synchronous control with very low skew across the device. flex 8000 devices support up to four individual global clock, clear, or preset control signals. if logic is required on a control signal, it can be generated in one or more les in any lab and driven into the local interconnect of the target lab. this process is called programmable inversion, and is available for all four lab control signals. logic element the logic element (le) is the smallest unit of logic in the flex 8000 architecture, with a compact size that provides efficient logic utilization. each le contains a 4-input lut, a programmable flipflop, a carry chain, and cascade chain. figure 3 shows a block diagram of an le. figure 3. flex 8000 le the lut is a function generator that can quickly compute any function of four variables. the programmable flipflop in the le can be configured for d, t, jk, or sr operation. the clock, clear, and preset control signals on the flipflop can be driven by dedicated input pins, general-purpose i/o pins, or any internal logic. for purely combinatorial functions, the flipflop is bypassed and the output of the lut goes directly to the output of the le. labctrl3 labctrl4 data 1 data 2 data 3 data 4 labctrl1 labctrl2 carry-in le-out clock select carry-out prn clrn dq dff look-up table (lut) clear/ preset logic carry chain cascade chain cascade-in cascade-out
8 altera corporation flex 8000 programmable logic device family data sheet the flex 8000 architecture provides two dedicated high-speed data paths?arry chains and cascade chains?hat connect adjacent les without using local interconnect paths. the carry chain supports high- speed counters and adders; the cascade chain implements wide-input functions with minimum delay. carry and cascade chains connect all les in an lab and all labs in the same row. heavy use of carry and cascade chains can reduce routing flexibility. therefore, the use of carry and cascade chains should be limited to speed-critical portions of a design. carry chain the carry chain provides a very fast (less than 1 ns) carry-forward function between les. the carry-in signal from a lower-order bit moves forward into the higher-order bit via the carry chain, and feeds into both the lut and the next portion of the carry chain. this feature allows the flex 8000 architecture to implement high-speed counters and adders of arbitrary width. the max+plus ii compiler can create carry chains automatically during design processing; designers can also insert carry chain logic manually during design entry. figure 4 shows how an n -bit full adder can be implemented in n + 1 les with the carry chain. one portion of the lut generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the le. the register is typically bypassed for simple adders, but can be used for an accumulator function. another portion of the lut and the carry chain logic generate the carry-out signal, which is routed directly to the carry-in signal of the next-higher-order bit. the final carry-out signal is routed to another le, where it can be used as a general-purpose signal. in addition to mathematical functions, carry chain logic supports very fast counters and comparators.
altera corporation 9 flex 8000 programmable logic device family data sheet flex 8000 3 figure 4. flex 8000 carry chain operation cascade chain with the cascade chain, the flex 8000 architecture can implement functions that have a very wide fan-in. adjacent luts can be used to compute portions of the function in parallel; the cascade chain serially connects the intermediate values. the cascade chain can use a logical and or logical or (via de morgan? inversion) to connect the outputs of adjacent les. each additional le provides four more inputs to the effective width of a function, with a delay as low as 0.6 ns per le. lu a1 b1 carry s1 le register a2 b2 carry chain s2 le register carry chain s n le register a n b n carry chain carry-out le n + 1 register carry-in lut lut lut
10 altera corporation flex 8000 programmable logic device family data sheet the max+plus ii compiler can create cascade chains automatically during design processing; designers can also insert cascade chain logic manually during design entry. cascade chains longer than eight les are automatically implemented by linking labs together. the last le of an lab cascades to the first le in the next lab in the row. figure 5 shows how the cascade function can connect adjacent les to form functions with a wide fan-in. these examples show functions of 4 n variables implemented with n les. for a device with an a-2 speed grade, the lut delay is approximately 1.6 ns; the cascade chain delay is 0.6 ns. with the cascade chain, 4.2 ns is needed to decode a 16-bit address. figure 5. flex 8000 cascade chain operation le operating modes the flex 8000 le can operate in one of four modes, each of which uses le resources differently. see figure 6 . in each mode, seven of the ten available inputs to the le?he four data inputs from the lab local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous le?re directed to different destinations to implement the desired logic function. the three remaining inputs to the le provide clock, clear, and preset control for the register. the max+plus ii software automatically chooses the appropriate mode for each application. design performance can also be enhanced by designing for the operating mode that supports the desired application. d[3..0] le1 lut d[7..4] le2 lut d[(4 n- 1)..4( n- 1)] le n lut d[3..0] lut d[7..4] lut d[(4 n- 1)..4( n- 1)] lut le1 le2 le n and cascade chain or cascade chain
altera corporation 11 flex 8000 programmable logic device family data sheet flex 8000 3 figure 6. flex 8000 le operating modes data 1 data 2 data 3 data 4 prn clrn dq 4-input lut carry-in cascade-out le-out cascade-in prn clrn dq cascade-out le-out cascade-in data 1 data 2 3-input lut carry-in 3-input lut carry-out normal mode arithmetic mode up/down clearable counter mode prn clrn dq 3-input lut carry-in cascade-in le-out 3-input lut carry-out 1 0 cascade-out data1 (ena) data2 (nclr) data3 (data) data4 (nload) prn clrn dq 3-input lut carry-in le-out 3-input lut carry-out 1 0 cascade-out data1 (ena) data2 (nclr) data3 (data) data4 (nload)
12 altera corporation flex 8000 programmable logic device family data sheet normal mode the normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. in normal mode, four data inputs from the lab local interconnect and the carry-in signal are the inputs to a 4-input lut. using a configurable sram bit, the max+plus ii compiler automatically selects the carry-in or the data3 signal as an input. the lut output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. the le-out signal?he data output of the le?s either the combinatorial output of the lut and cascade chain, or the data output ( q) of the programmable register. arithmetic mode the arithmetic mode offers two 3-input luts that are ideal for implementing adders, accumulators, and comparators. one lut provides a 3-bit function; the other generates a carry bit. as shown in figure 6 , the first lut uses the carry-in signal and two data inputs from the lab local interconnect to generate a combinatorial or registered output. for example, in an adder, this output is the sum of three bits: a , b , and the carry-in. the second lut uses the same three signals to generate a carry-out signal, thereby creating a carry chain. the arithmetic mode also supports a cascade chain. up/down counter mode the up/down counter mode offers counter enable, synchronous up/down control, and data loading options. these control signals are generated by the data inputs from the lab local interconnect, the carry-in signal, and output feedback from the programmable register. two 3-input luts are used: one generates the counter data, and the other generates the fast carry bit. a 2-to-1 multiplexer provides synchronous loading. data can also be loaded asynchronously with the clear and preset register control signals, without using the lut resources. clearable counter mode the clearable counter mode is similar to the up/down counter mode, but supports a synchronous clear instead of the up/down control; the clear function is substituted for the cascade-in signal in the up/down counter mode. two 3-input luts are used: one generates the counter data, and the other generates the fast carry bit. synchronous loading is provided by a 2-to-1 multiplexer, and the output of this multiplexer is and ed with a synchronous clear.
altera corporation 13 flex 8000 programmable logic device family data sheet flex 8000 3 internal tri-state emulation internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus. in a physical tri-state bus, the tri-state buffers?output enable signals select the signal that drives the bus. however, if multiple output enable signals are active, contending signals can be driven onto the bus. conversely, if no output enable signals are active, the bus will float. internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. the max+plus ii software automatically implements tri-state bus functionality with a multiplexer. clear & preset logic control logic for the programmable register? clear and preset functions is controlled by the data3 , labctrl1 , and labctrl2 inputs to the le. the clear and preset control structure of the le is used to asynchronously load signals into a register. the register can be set up so that labctrl1 implements an asynchronous load. the data to be loaded is driven to data3 ; when labctrl1 is asserted, data3 is loaded into the register. during compilation, the max+plus ii compiler automatically selects the best control signal implementation. because the clear and preset functions are active-low, the compiler automatically assigns a logic high to an unused clear or preset. the clear and preset logic is implemented in one of the following six asynchronous modes, which are chosen during design entry. lpm functions that use registers will automatically use the correct asynchronous mode. see figure 7 . n clear only n preset only n clear and preset n load with clear n load with preset n load without clear or preset
14 altera corporation flex 8000 programmable logic device family data sheet figure 7. flex 8000 le asynchronous clear & preset modes asynchronous load with preset not not labctrl1 (asynchronous load) labctrl2 (preset) data 3 (data) prn clrn d q asynchronous load without clear or preset labctrl1 (asynchronous load) data 3 (data) not not prn clrn d q labctrl1 (asynchronous load) asynchronous load with clear data 3 (data) labctrl2 (clear) not not prn clrn d q labctrl1 or labctrl2 labctrl1 or labctrl2 labctrl1 labctrl2 asynchronous clear asynchronous preset asynchronous clear & preset prn clrn d q vcc prn clrn d q prn clrn d q
altera corporation 15 flex 8000 programmable logic device family data sheet flex 8000 3 asynchronous clear a register is cleared by one of the two labctrl signals. when the clrn port receives a low signal, the register is set to zero. asynchronous preset an asynchronous preset is implemented as either an asynchronous load or an asynchronous clear. if data3 is tied to vcc , asserting labctrll asynchronously loads a 1 into the register. alternatively, the max+plus ii software can provide preset control by using the clear and inverting the input and output of the register. inversion control is available for the inputs to both les and ioes. therefore, if a register is preset by only one of the two labctrl signals, the data3 input is not needed and can be used for one of the le operating modes. asynchronous clear & preset when implementing asynchronous clear and preset, labctrl1 controls the preset and labctrl2 controls the clear. the data3 input is tied to vcc ; therefore, asserting labctrl1 asynchronously loads a 1 into the register, effectively presetting the register. asserting labctrl2 clears the register. asynchronous load with clear when implementing an asynchronous load with the clear, labctrl1 implements the asynchronous load of data3 by controlling the register preset and clear. labctrl2 implements the clear by controlling the register clear. asynchronous load with preset when implementing an asynchronous load in conjunction with a preset, the max+plus ii software provides preset control by using the clear and inverting the input and output of the register. asserting labctrl2 clears the register, while asserting labctrl1 loads the register. the max+plus ii software inverts the signal that drives the data3 signal to account for the inversion of the register? output. asynchronous load without clear or preset when implementing an asynchronous load without the clear or preset, labctrl1 implements the asynchronous load of data3 by controlling the register preset and clear.
16 altera corporation flex 8000 programmable logic device family data sheet fasttrack interconnect in the flex 8000 architecture, connections between les and device i/o pins are provided by the fasttrack interconnect, a series of continuous horizontal (row) and vertical (column) routing channels that traverse the entire flex 8000 device. this device-wide routing structure provides predictable performance even in complex designs. in contrast, the segmented routing structure in fpgas requires switch matrices to connect a variable number of routing paths, which increases the delays between logic resources and reduces performance. the labs within flex 8000 devices are arranged into a matrix of columns and rows. each row of labs has a dedicated row interconnect that routes signals both into and out of the labs in the row. the row interconnect can then drive i/o pins or feed other labs in the device. figure 8 shows how an le drives the row and column interconnect. figure 8. flex 8000 lab connections to row & column interconnect le1 le2 row channels 16 column channels each le drives up to two column channels. to local feedback to local feedback each le drives one row channel. note (1) note: (1) see table 4 for the number of row channels.
altera corporation 17 flex 8000 programmable logic device family data sheet flex 8000 3 each le in an lab can drive up to two separate column interconnect channels. therefore, all 16 available column channels can be driven by the lab. the column channels run vertically across the entire device, and share access to labs in the same column but in different rows. the max+plus ii compiler chooses which les must be connected to a column channel. a row interconnect channel can be fed by the output of the le or by two column channels. these three signals feed a multiplexer that connects to a specific row channel. each le is connected to one 3-to-1 multiplexer. in an lab, the multiplexers provide all 16 column channels with access to 8 row channels. each column of labs has a dedicated column interconnect that routes signals out of the labs into the column. the column interconnect can then drive i/o pins or feed into the row interconnect to route the signals to other labs in the device. a signal from the column interconnect, which can be either the output of an le or an input from an i/o pin, must transfer to the row interconnect before it can enter an lab. table 4 summarizes the fasttrack interconnect resources available in each flex 8000 device. figure 9 shows the interconnection of four adjacent labs, with row, column, and local interconnects, as well as the associated cascade and carry chains. table 4. flex 8000 fasttrack interconnect resources device rows channels per row columns channels per column epf8282a epf8282av 2 168 13 16 epf8452a 2 168 21 16 epf8636a 3 168 21 16 EPF8820A 4 168 21 16 epf81188a 6 168 21 16 epf81500a 6 216 27 16
18 altera corporation flex 8000 programmable logic device family data sheet figure 9. flex 8000 device interconnect resources each lab is named according to its physical row (a, b, c, etc.) and column (1, 2, 3, etc.) position within the device. i/o element an ioe contains a bidirectional i/o buffer and a register that can be used either as an input register for external data that requires a fast setup time, or as an output register for data that requires fast clock-to-output performance. ioes can be used as input, output, or bidirectional pins. the max+plus ii compiler uses the programmable inversion option to automatically invert signals from the row and column interconnect where appropriate. figure 10 shows the ioe block diagram. ioe ioe ioe ioe lab a1 lab a2 lab b1 lab b2 lab local interconnect column interconnect row interconnect cascade & carry chain ioe ioe ioe ioe ioe ioe ioe ioe see figure 10 for details. see figure 11 for details. 1 8 1 8 1 8 ioe ioe 1 8 ioe ioe
altera corporation 19 flex 8000 programmable logic device family data sheet flex 8000 3 figure 10. flex 8000 ioe numbers in parentheses are for epf81500a devices only. row-to-ioe connections figure 11 illustrates the connection between row interconnect channels and ioes. an input signal from an ioe can drive two separate row channels. when an ioe is used as an output, the signal is driven by an n -to-1 multiplexer that selects the row channels. the size of the multiplexer varies with the number of columns in a device. epf81500a devices use a 27-to-1 multiplexer; epf81188a, EPF8820A, epf8636a, and epf8452a devices use a 21-to-1 multiplexer; and epf8282a and epf8282av devices use a 13-to-1 multiplexer. eight ioes are connected to each side of the row channels. from row or column interconnect slew-rate control to row or column interconnect i/o controls 6 (6) clrn dq programmable inversion clr0 clr1/oe0 clk1/oe1 clk0 (oe [4..9]) oe2 oe3 vcc vcc
20 altera corporation flex 8000 programmable logic device family data sheet figure 11. flex 8000 row-to-ioe connections note: (1) n = 13 for epf8282a and epf8282av devices. n = 21 for epf8452a, epf8636a, EPF8820A, and epf81188a devices. n = 27 for epf81500a devices. column-to-ioe connections two ioes are located at the top and bottom of the column channels (see figure 12 ). when an ioe is used as an input, it can drive up to two separate column channels. the output signal to an ioe can choose from 8 of the 16 column channels through an 8-to-1 multiplexer. ioe 1 ioe 2 ioe 3 ioe 4 ioe 5 ioe 6 ioe 7 ioe 8 n n n n n n n n 2 2 2 2 2 2 2 2 22 2 2 2 2 2 2 row interconnect 168 (216) 168 (216) each ioe can drive up to two row channels. each ioe is driven by an n-to-1 multiplexer. numbers in parentheses are for epf81500a devices. see note (1) .
altera corporation 21 flex 8000 programmable logic device family data sheet flex 8000 3 figure 12. flex 8000 column-to-ioe connections in addition to general-purpose i/o pins, flex 8000 devices have four dedicated input pins. these dedicated inputs provide low-skew, device- wide signal distribution, and are typically used for global clock, clear, and preset control signals. the signals from the dedicated inputs are available as control signals for all labs and i/o elements in the device. the dedicated inputs can also be used as general-purpose data inputs because they can feed the local interconnect of each lab in the device. signals enter the flex 8000 device either from the i/o pins that provide general-purpose input capability or from the four dedicated inputs. the ioes are located at the ends of the row and column interconnect channels. i/o pins can be used as input, output, or bidirectional pins. each i/o pin has a register that can be used either as an input register for external data that requires fast setup times, or as an output register for data that requires fast clock-to-output performance. the max+plus ii compiler uses the programmable inversion option to automatically invert signals from the row and column interconnect when appropriate. the clock, clear, and output enable controls for the ioes are provided by a network of i/o control signals. these signals can be supplied by either the dedicated input pins or by internal logic. the ioe control-signal paths are designed to minimize the skew across the device. all control-signal sources are buffered onto high-speed drivers that drive the signals around the periphery of the device. this ?eripheral bus?can be configured to provide up to four output enable signals (10 in epf81500a devices), and up to two clock or clear signals. figure 13 shows how two output enable signals are shared with one clock and one clear signal. ioe ioe 8 8 16 column interconnect each ioe is driven by an 8-to-1 multiplexer. each ioe can drive up to two column signals.
22 altera corporation flex 8000 programmable logic device family data sheet the signals for the peripheral bus can be generated by any of the four dedicated inputs or signals on the row interconnect channels, as shown in figure 13 . the number of row channels in a row that can drive the peripheral bus correlates to the number of columns in the flex 8000 device. epf8282a and epf8282av devices use 13 channels; epf8452a, epf8636a, EPF8820A, and epf81188a devices use 21 channels; and epf81500a devices use 27 channels. the first le in each lab is the source of the row channel signal. the six peripheral control signals (12 in epf81500a devices) can be accessed by each ioe. figure 13. flex 8000 peripheral bus note: (1) n = 13 for epf8282a and epf8282av devices. n = 21 for epf8452a, epf8636a, EPF8820A, and epf81188a devices. n = 27 for epf81500a devices. dedicated inputs 4 1 2 n peripheral control signals clr0 clr1/oe0 clk0 clk1/oe1 row channels programmable inversion oe2 oe3 (oe[4..9]) note (1) numbers in parentheses are for epf81500a devices.
altera corporation 23 flex 8000 programmable logic device family data sheet flex 8000 3 table 5 lists the source of the peripheral control signal for each flex 8000 device by row. output con?uration this section discusses slew-rate control and multivolt i/o interface operation for flex 8000 devices. slew-rate control the output buffer in each ioe has an adjustable output slew rate that can be configured for low-noise or high-speed performance. a slow slew rate reduces system noise by slowing signal transitions, adding a maximum delay of 3.5 ns. the slow slew-rate setting affects only the falling edge of a signal. the fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a global basis. f for more information on high-speed system design, go to application note 75 (high-speed board designs) in this data book. table 5. row sources of flex 8000 peripheral control signals peripheral control signal epf8282a epf8282av epf8452a epf8636a EPF8820A epf81188a epf81500a clk0 row a row a row a row a row e row e clk1/oe1 row b row b row c row c row b row b clr0 row a row a row b row b row f row f clr1/oe0 row b row b row c row d row c row c oe2 row a row a row a row a row d row a oe3 row b row b row b row b row a row a oe4 row b oe5 row c oe6 row d oe7 row d oe8 row e oe9 row f
24 altera corporation flex 8000 programmable logic device family data sheet multivolt i/o interface the flex 8000 device architecture supports the multivolt i/o interface feature, which allows epf81500a, epf81188a, EPF8820A, and epf8636a devices to interface with systems with differing supply voltages. these devices in all packages?xcept for epf8636a devices in 84-pin plcc packages?an be set for 3.3-v or 5.0-v i/o pin operation. these devices have one set of v cc pins for internal operation and input buffers ( vccint ), and another set for i/o output drivers ( vccio ). the vccint pins must always be connected to a 5.0-v power supply. with a 5.0-v v ccint level, input voltages are at ttl levels and are therefore compatible with 3.3-v and 5.0-v inputs. the vccio pins can be connected to either a 3.3-v or 5.0-v power supply, depending on the output requirements. when the vccio pins are connected to a 5.0-v power supply, the output levels are compatible with 5.0-v systems. when the vccio pins are connected to a 3.3-v power supply, the output high is at 3.3 v and is therefore compatible with 3.3-v or 5.0-v systems. devices operating with v ccio levels lower than 4.75 v incur a nominally greater timing delay of t od2 instead of t od1 . see table 7 on page 26 . ieee 1149.1 (jtag) boundary-scan support the epf8282a, epf8282av, epf8636a, EPF8820A, and epf81500a devices provide jtag bst circuitry. flex 8000 devices with jtag circuitry support the jtag instructions shown in table 6 . figure 14 shows the timing requirements for the jtag signals. table 6. epf8282a, epf8282av, epf8636a, EPF8820A & epf81500a jtag instructions jtag instruction description sample/preload allows a snapshot of the signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. extest allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through the selected device to adjacent devices during normal device operation.
altera corporation 25 flex 8000 programmable logic device family data sheet flex 8000 3 figure 14. epf8282a, epf8282av, epf8636a, EPF8820A & epf81500a jtag waveforms table 7 shows the timing parameters and values for epf8282a, epf8282av, epf8636a, EPF8820A, and epf81500a devices. tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
26 altera corporation flex 8000 programmable logic device family data sheet f for detailed information on jtag operation in flex 8000 devices, refer to application note 39 (jtag boundary-scan testing in altera devices) . generic testing each flex 8000 device is functionally tested and specified by altera. complete testing of each configurable sram bit and all logic functionality ensures 100 % configuration yield. ac test measurements for flex 8000 devices are made under conditions equivalent to those shown in figure 15 . designers can use multiple test patterns to configure devices during all stages of the production flow. table 7. jtag timing parameters & values symbol parameter epf8282a epf8282av epf8636a EPF8820A epf81500a unit min max t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high-impedance to valid output 25 ns t jpxz jtag port valid output to high-impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 35 ns t jszx update register high-impedance to valid output 35 ns t jsxz update register valid output to high-impedance 35 ns
altera corporation 27 flex 8000 programmable logic device family data sheet flex 8000 3 figure 15. flex 8000 ac test conditions operating conditions the following tables provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 5.0-v and 3.3-v flex 8000 devices. flex 8000 5.0-v device absolute maximum ratings note (1) flex 8000 5.0-v device recommended operating conditions vcc to test system c1 (includes jig capacitance) device input rise and fall times < 3 ns 464 w (703 w ) device output 250 w (8.06 k w ) power supply transients can affect ac measurements. simultaneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be performed under ac conditions. large-amplitude, fast-ground-current transients normally occur as the device outputs discharge the load capacitances. when these transients ?w through the parasitic inductance between the device ground pin and the test system ground, signi?ant reductions in observable noise immunity can result. numbers in symbol parameter conditions min max unit v cc supply voltage with respect to ground, note (2) ?.0 7.0 v v i dc input voltage ?.0 7.0 v i out dc output current, per pin ?5 25 ma t stg storage temperature no bias ?5 150 ?c t amb ambient temperature under bias ?5 135 ?c t j junction temperature ceramic packages, under bias 150 ?c pqfp and rqfp, under bias 135 ?c symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers notes (3) , (4) 4.75 (4.50) 5.25 (5.50) v v ccio supply voltage for output buffers, 5.0-v operation notes (3) , (4) 4.75 (4.50) 5.25 (5.50) v supply voltage for output buffers, 3.3-v operation notes (3) , (4) 3.00 (3.00) 3.60 (3.60) v v i input voltage 0 v ccint v v o output voltage 0 v ccio v t a operating temperature for commercial use 0 70 c for industrial use ?0 85 ?c t r input rise time 40 ns t f input fall time 40 ns
28 altera corporation flex 8000 programmable logic device family data sheet flex 8000 5.0-v device dc operating conditions notes (5) , (6) flex 8000 5.0-v device capacitance note (8) symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 v ccint + 0.3 v v il low-level input voltage ?.3 0.8 v v oh 5.0-v high-level ttl output voltage i oh = ? ma dc, note (7) v ccio = 4.75 v 2.4 v 3.3-v high-level ttl output voltage i oh = ? ma dc, note (7) v ccio = 3.00 v 2.4 v 3.3-v high-level cmos output voltage i oh = ?.1 ma dc, note (7) v ccio = 3.00 v v ccio ?0.2 v v ol 5.0-v low-level ttl output voltage i ol = 12 ma dc, note (7) v ccio = 4.75 v 0.45 v 3.3-v low-level ttl output voltage i ol = 12 ma dc, note (7) v ccio = 3.00 v 0.45 v 3.3-v low-level cmos output voltage i ol = 0.1 ma dc, note (7) v ccio = 3.00 v 0.2 v i i input leakage current v i = v cc or ground ?0 10 ? i oz tri-state output off-state current v o = v cc or ground ?0 40 ? i cc0 v cc supply current (standby) v i = ground, no load 0.5 10 ma symbol parameter conditions min max unit c in input capacitance v in = 0 v, f = 1.0 mhz 10 pf c out output capacitance v out = 0 v, f = 1.0 mhz 10 pf
altera corporation 29 flex 8000 programmable logic device family data sheet flex 8000 3 notes to tables: (1) see the operating requirements for altera devices data sheet in this data book. (2) minimum dc input is ?.3 v. during transitions, the inputs may undershoot to ?.0 v or overshoot to 7.0 v for periods shorter than 20 ns under no-load conditions. (3) the maximum v cc rise time is 100 ms. (4) numbers in parentheses are for industrial-temperature-range devices. (5) typical values are for t a = 25 c and v cc = 5.0 v. (6) these values are specified under ?lex 8000 5.0-v device recommended operating conditions on page 27 . (7) the i oh parameter refers to high-level ttl or cmos output current; the i ol parameter refers to low-level ttl or cmos output current. (8) capacitance is sample-tested only. flex 8000 3.3-v device absolute maximum ratings note (1) flex 8000 3.3-v device recommended operating conditions flex 8000 3.3-v device dc operating conditions note (4) symbol parameter conditions min max unit v cc supply voltage with respect to ground, note (2) ?.0 5.3 v v i dc input voltage ?.0 5.3 v i out dc output current, per pin ?5 25 ma t stg storage temperature no bias ?5 150 ?c t amb ambient temperature under bias ?5 135 ?c t j junction temperature plastic packages, under bias 135 ?c symbol parameter conditions min max unit v cc supply voltage note (3) 3.0 3.6 v v i input voltage 0v cc v v o output voltage 0v cc v t a operating temperature for commercial use 0 70 c t r input rise time 40 ns t f input fall time 40 ns symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 v cc + 0.3 v v il low-level input voltage ?.3 0.8 v v oh high-level output voltage i oh = ?.1 ma dc, note (5) v cc ?0.2 v v ol low-level output voltage i ol = 4 ma dc, note (5) 0.45 v i i input leakage current v i = v cc or ground ?0 10 ? i oz tri-state output off-state current v o = v cc or ground ?0 40 ? i cc0 v cc supply current (standby) v i = ground, no load, note (6) 0.3 10 ma
30 altera corporation flex 8000 programmable logic device family data sheet flex 8000 3.3-v device capacitance note (7) notes to tables: (1) see the operating requirements for altera devices data sheet in this data book. (2) minimum dc input is ?.3 v. during transitions, the inputs may undershoot to ?.0 v or overshoot to 5.3 v for periods shorter than 20 ns under no-load conditions. (3) the maximum v cc rise time is 100 ms. v cc must rise monotonically. (4) these values are specified under ?lex 8000 3.3-v device recommended operating conditions on page 29 . (5) the i oh parameter refers to high-level ttl output current; the i ol parameter refers to low-level ttl output current. (6) typical values are for t a = 25?c and v cc = 3.3 v. (7) capacitance is sample-tested only. figures 16 and 17 show the typical output drive characteristics of 5.0-v flex 8000 devices. the output driver is compliant with the pci local bus specification, revision 2.1 . figure 16. output drive characteristics of 5.0-v flex 8000 devices (except epf8282a) symbol parameter conditions min max unit c in input capacitance v in = 0 v, f = 1.0 mhz 10 pf c out output capacitance v out = 0 v, f = 1.0 mhz 10 pf v o output voltage (v) 1234 5 0 1 0 0 1 5 0 200 v ccint = 5.0 v v ccio = 3.3 v i ol i oh room temperatur e i o output current (ma) typ. v o output voltage (v) 12345 50 100 150 200 v ccint = 5.0 v v ccio = 5.0 v room temperature i ol i oh i o output current (ma) typ.
altera corporation 31 flex 8000 programmable logic device family data sheet flex 8000 3 figure 17. output drive characteristics of epf8282a devices with 5.0-v v ccio figure 18 shows the typical output drive characteristics of epf8282av devices. figure 18. output drive characteristics of epf8282av devices v o output voltage (v) 12345 30 60 90 150 120 v cc = 5.0 v i ol i oh room temperature i o output current (ma) typ. v o output voltage (v) 1234 25 50 75 100 v cc = 3.3 v i ol i oh room temperature i o output current (ma) typ.
32 altera corporation flex 8000 programmable logic device family data sheet timing model the continuous, high-performance fasttrack interconnect routing structure ensures predictable performance and accurate simulation and timing analysis. this predictable performance contrasts with that of fpgas, which use a segmented connection scheme and hence have unpredictable performance. timing simulation and delay prediction are available with the max+plus ii simulator and timing analyzer, or with industry-standard eda tools. the simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post- synthesis timing simulation with 0.1-ns resolution. the timing analyzer provides point-to-point timing delay information, setup and hold time prediction, and device-wide performance analysis. tables 8 through 11 describe the flex 8000 timing parameters and their symbols. table 8. flex 8000 internal timing parameters note (1) symbol parameter t iod ioe register data delay t ioc ioe register control signal delay t ioe output enable delay t ioco ioe register clock-to-output delay t iocomb ioe combinatorial delay t iosu ioe register setup time before clock; ioe register recovery time after asynchronous clear t ioh ioe register hold time after clock t ioclr ioe register clear delay t in input pad and buffer delay t od1 output buffer and pad delay, slow slew rate = off, v ccio = 5.0 v, c1 = 35 pf, note (2) t od2 output buffer and pad delay, slow slew rate = off, v ccio = 3.3 v, c1 = 35 pf, note (2) t od3 output buffer and pad delay, slow slew rate = on, c1 = 35 pf, note (3) t xz output buffer disable delay, c1 = 5 pf t zx1 output buffer enable delay, slow slew rate = off, v ccio = 5.0 v, c1 = 35 pf, note (2) t zx2 output buffer enable delay, slow slew rate = off, v ccio = 3.3 v, c1 = 35 pf, note (2) t zx3 output buffer enable delay, slow slew rate = on, c1 = 35 pf, note (3)
altera corporation 33 flex 8000 programmable logic device family data sheet flex 8000 3 table 9. flex 8000 le timing parameters note (1) symbol parameter t lut lut delay for data-in t clut lut delay for carry-in t rlut lut delay for le register feedback t gate cascade gate delay t casc cascade chain routing delay t cico carry-in to carry-out delay t cgen data-in to carry-out delay t cgenr le register feedback to carry-out delay t c le register control signal delay t ch le register clock high time t cl le register clock low time t co le register clock-to-output delay t comb combinatorial delay t su le register setup time before clock; le register recovery time after asynchronous preset, clear, or load t h le register hold time after clock t pre le register preset delay t clr le register clear delay table 10. flex 8000 interconnect timing parameters note (1) symbol parameter t labcasc cascade delay between les in different labs t labcarry carry delay between les in different labs t local lab local interconnect delay t row row interconnect routing delay, note (4) t col column interconnect routing delay t din_c dedicated input to le control delay t din_d dedicated input to le data delay, note (4) t din_io dedicated input to ioe control delay table 11. flex 8000 external reference timing characteristics note (5) symbol parameter t drr register-to-register delay via 4 les, 3 row interconnects, and 4 local interconnects, note (6) t odh output data hold time after clock, note (7)
34 altera corporation flex 8000 programmable logic device family data sheet notes to tables: (1) internal timing parameters cannot be measured explicitly. they are worst-case delays based on testable and external parameters specified by altera. internal timing parameters should be used for estimating device performance. post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. (2) these values are specified under ?lex 8000 3.3-v device recommended operating conditions on page 29 . (3) for the t od3 and t zx3 parameters, v ccio = 3.3 v or 5.0 v. (4) the t row and t din_d delays are worst-case values for typical applications. post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. (5) external reference timing characteristics are factory-tested, worst-case values specified by altera. a representative subset of signal paths is tested to approximate typical device applications. (6) for more information on test conditions, see application note 76 ( understanding flex 8000 timing ) in this data book. (7) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies to global and non-global clocking, and for le and i/o element registers. the flex 8000 timing model shows the delays for various paths and functions in the circuit. see figure 19 . this model contains three distinct parts: the le; the ioe; and the interconnect, including the row and column fasttrack interconnect, lab local interconnect, and carry and cascade interconnect paths. each parameter shown in figure 19 is expressed as a worst-case value in the ?iming parameters?tables in this data sheet. hand-calculations that use the flex 8000 timing model and these timing parameters can be used to estimate flex 8000 device performance. timing simulation or timing analysis after compilation is required to determine the final worst-case performance. table 12 summarizes the interconnect paths shown in figure 19 . f for more information on timing parameters, go to application note 76 (understanding flex 8000 timing) in this data book. table 12. flex 8000 timing model interconnect paths source destination total delay le-out le in same lab t local le-out le in same row, different lab t row + t local le-out le in different row t col + t row + t local le-out ioe on column t col le-out ioe on row t row ioe on row le in same row t row + t local ioe on column any le t col + t row + t local
altera corporation 35 flex 8000 programmable logic device family data sheet flex 8000 3 figure 19. flex 8000 timing model t co t comb t su t h t pre t clr register delays lut delay t lut t rlut t clut carry chain delay register control carry-in from previous le cascade-in from previous le le-out t labcasc t labcarry cascade-out to next le in next lab carry-out to next le in next lab le dedicated input delays i/o pin t ioc t ioe t in t iod i/o register delays output data delay i/o register control input delay output delays t ioco t iocomb t iosu t ioh t ioclr t od1 t od2 t od3 t xz t zx1 t zx2 t zx3 ioe data-in t col t row t local carry-out to next le in same lab cascade-out to next le in same lab cascade gate delay t gate t cgen t cgenr t cico t din_d t din_c t din_io t casc cascade routing delay t c
36 altera corporation flex 8000 programmable logic device family data sheet epf8282a internal timing parameters epf8282a i/o element timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t iod 0.7 0.8 0.9 ns t ioc 1.7 1.8 1.9 ns t ioe 1.7 1.8 1.9 ns t ioco 1.0 1.0 1.0 ns t iocomb 0.3 0.2 0.1 ns t iosu 1.4 1.6 1.8 ns t ioh 0.0 0.0 0.0 ns t ioclr 1.2 1.2 1.2 ns t in 1.5 1.6 1.7 ns t od1 1.1 1.4 1.7 ns t od2 ns t od3 4.6 4.9 5.2 ns t xz 1.4 1.6 1.8 ns t zx1 1.4 1.6 1.8 ns t zx2 ns t zx3 4.9 5.1 5.3 ns epf8282a interconnect timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t labcasc 0.3 0.3 0.4 ns t labcarry 0.3 0.3 0.4 ns t local 0.5 0.6 0.8 ns t row 4.2 4.2 4.2 ns t col 2.5 2.5 2.5 ns t din_c 5.0 5.0 5.5 ns t din_d 7.2 7.2 7.2 ns t din_io 5.0 5.0 5.5 ns
altera corporation 37 flex 8000 programmable logic device family data sheet flex 8000 3 epf8282a external timing parameters epf8282a le timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t lut 2.0 2.5 3.2 ns t clut 0.0 0.0 0.0 ns t rlut 0.9 1.1 1.5 ns t gate 0.0 0.0 0.0 ns t casc 0.6 0.7 0.9 ns t cico 0.4 0.5 0.6 ns t cgen 0.4 0.5 0.7 ns t cgenr 0.9 1.1 1.5 ns t c 1.6 2.0 2.5 ns t ch 4.0 4.0 4.0 ns t cl 4.0 4.0 4.0 ns t co 0.4 0.5 0.6 ns t comb 0.4 0.5 0.6 ns t su 0.8 1.1 1.2 ns t h 0.9 1.1 1.5 ns t pre 0.6 0.7 0.8 ns t clr 0.6 0.7 0.8 ns symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t drr 15.8 19.8 24.8 ns t odh 1.0 1.0 1.0 ns
38 altera corporation flex 8000 programmable logic device family data sheet epf8282av internal timing parameters epf8282av i/o element timing parameters symbol a-3 speed grade a-4 speed grade unit min max min max t iod 0.9 2.2 ns t ioc 1.9 2.0 ns t ioe 1.9 2.0 ns t ioco 1.0 2.0 ns t iocomb 0.1 0.0 ns t iosu 1.8 2.8 ns t ioh 0.0 0.2 ns t ioclr 1.2 2.3 ns t in 1.7 3.4 ns t od1 1.7 4.1 ns t od2 ns t od3 5.2 7.1 ns t xz 1.8 4.3 ns t zx1 1.8 4.3 ns t zx2 ns t zx3 5.3 8.3 ns epf8282av interconnect timing parameters symbol a-3 speed grade a-4 speed grade unit min max min max t labcasc 0.4 1.3 ns t labcarry 0.4 0.8 ns t local 0.8 1.5 ns t row 4.2 6.3 ns t col 2.5 3.8 ns t din_c 5.5 8.0 ns t din_d 7.2 10.8 ns t din_io 5.5 9.0 ns
altera corporation 39 flex 8000 programmable logic device family data sheet flex 8000 3 epf8282av external timing parameters epf8282av logic element timing parameters symbol a-3 speed grade a-4 speed grade unit min max min max t lut 3.2 7.3 ns t clut 0.0 1.4 ns t rlut 1.5 5.1 ns t gate 0.0 0.0 ns t casc 0.9 2.8 ns t cico 0.6 1.5 ns t cgen 0.7 2.2 ns t cgenr 1.5 3.7 ns t c 2.5 4.7 ns t ch 4.0 6.0 ns t cl 4.0 6.0 ns t co 0.6 0.9 ns t comb 0.6 0.9 ns t su 1.2 2.4 ns t h 1.5 4.6 ns t pre 0.8 1.3 ns t clr 0.8 1.3 ns symbol a-3 speed grade a-4 speed grade unit min max min max t drr 24.8 50.1 ns t odh 1.0 1.0 ns
40 altera corporation flex 8000 programmable logic device family data sheet epf8452a internal timing parameters epf8452a i/o element timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t iod 0.7 0.8 0.9 ns t ioc 1.7 1.8 1.9 ns t ioe 1.7 1.8 1.9 ns t ioco 1.0 1.0 1.0 ns t iocomb 0.3 0.2 0.1 ns t iosu 1.4 1.6 1.8 ns t ioh 0.0 0.0 0.0 ns t ioclr 1.2 1.2 1.2 ns t in 1.5 1.6 1.7 ns t od1 1.1 1.4 1.7 ns t od2 ns t od3 4.6 4.9 5.2 ns t xz 1.4 1.6 1.8 ns t zx1 1.4 1.6 1.8 ns t zx2 ns t zx3 4.9 5.1 5.3 ns epf8452a interconnect timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t labcasc 0.3 0.4 0.4 ns t labcarry 0.3 0.4 0.4 ns t local 0.5 0.5 0.7 ns t row 5.0 5.0 5.0 ns t col 3.0 3.0 3.0 ns t din_c 5.0 5.0 5.5 ns t din_d 7.0 7.0 7.5 ns t din_io 5.0 5.0 5.5 ns
altera corporation 41 flex 8000 programmable logic device family data sheet flex 8000 3 epf8452a external timing parameters epf8452a le timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t lut 2.0 2.3 3.0 ns t clut 0.0 0.2 0.1 ns t rlut 0.9 1.6 1.6 ns t gate 0.0 0.0 0.0 ns t casc 0.6 0.7 0.9 ns t cico 0.4 0.5 0.6 ns t cgen 0.4 0.9 0.8 ns t cgenr 0.9 1.4 1.5 ns t c 1.6 1.8 2.4 ns t ch 4.0 4.0 4.0 ns t cl 4.0 4.0 4.0 ns t co 0.4 0.5 0.6 ns t comb 0.4 0.5 0.6 ns t su 0.8 1.0 1.1 ns t h 0.9 1.1 1.4 ns t pre 0.6 0.7 0.8 ns t clr 0.6 0.7 0.8 ns symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t drr 16.0 20.0 25.0 ns t odh 1.0 1.0 1.0 ns
42 altera corporation flex 8000 programmable logic device family data sheet epf8636a internal timing parameters epf8636a i/o element timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t iod 0.7 0.8 0.9 ns t ioc 1.7 1.8 1.9 ns t ioe 1.7 1.8 1.9 ns t ioco 1.0 1.0 1.0 ns t iocomb 0.3 0.2 0.1 ns t iosu 1.4 1.6 1.8 ns t ioh 0.0 0.0 0.0 ns t ioclr 1.2 1.2 1.2 ns t in 1.5 1.6 1.7 ns t od1 1.1 1.4 1.7 ns t od2 1.6 1.9 2.2 ns t od3 4.6 4.9 5.2 ns t xz 1.4 1.6 1.8 ns t zx1 1.4 1.6 1.8 ns t zx2 1.9 2.1 2.3 ns t zx3 4.9 5.1 5.3 ns epf8636a interconnect timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t labcasc 0.3 0.4 0.4 ns t labcarry 0.3 0.4 0.4 ns t local 0.5 0.5 0.7 ns t row 5.0 5.0 5.0 ns t col 3.0 3.0 3.0 ns t din_c 5.0 5.0 5.5 ns t din_d 7.0 7.0 7.5 ns t din_io 5.0 5.0 5.5 ns
altera corporation 43 flex 8000 programmable logic device family data sheet flex 8000 3 epf8636a external timing parameters epf8636a le timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t lut 2.0 2.3 3.0 ns t clut 0.0 0.2 0.1 ns t rlut 0.9 1.6 1.6 ns t gate 0.0 0.0 0.0 ns t casc 0.6 0.7 0.9 ns t cico 0.4 0.5 0.6 ns t cgen 0.4 0.9 0.8 ns t cgenr 0.9 1.4 1.5 ns t c 1.6 1.8 2.4 ns t ch 4.0 4.0 4.0 ns t cl 4.0 4.0 4.0 ns t co 0.4 0.5 0.6 ns t comb 0.4 0.5 0.6 ns t su 0.8 1.0 1.1 ns t h 0.9 1.1 1.4 ns t pre 0.6 0.7 0.8 ns t clr 0.6 0.7 0.8 ns symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t drr 16.0 20.0 25.0 ns t odh 1.0 1.0 1.0 ns
44 altera corporation flex 8000 programmable logic device family data sheet EPF8820A internal timing parameters EPF8820A i/o element timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t iod 0.7 0.8 0.9 ns t ioc 1.7 1.8 1.9 ns t ioe 1.7 1.8 1.9 ns t ioco 1.0 1.0 1.0 ns t iocomb 0.3 0.2 0.1 ns t iosu 1.4 1.6 1.8 ns t ioh 0.0 0.0 0.0 ns t ioclr 1.2 1.2 1.2 ns t in 1.5 1.6 1.7 ns t od1 1.1 1.4 1.7 ns t od2 1.6 1.9 2.2 ns t od3 4.6 4.9 5.2 ns t xz 1.4 1.6 1.8 ns t zx1 1.4 1.6 1.8 ns t zx2 1.9 2.1 2.3 ns t zx3 4.9 5.1 5.3 ns EPF8820A interconnect timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t labcasc 0.3 0.3 0.4 ns t labcarry 0.3 0.3 0.4 ns t local 0.5 0.6 0.8 ns t row 5.0 5.0 5.0 ns t col 3.0 3.0 3.0 ns t din_c 5.0 5.0 5.5 ns t din_d 7.0 7.0 7.5 ns t din_io 5.0 5.0 5.5 ns
altera corporation 45 flex 8000 programmable logic device family data sheet flex 8000 3 EPF8820A external timing parameters EPF8820A le timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t lut 2.0 2.5 3.2 ns t clut 0.0 0.0 0.0 ns t rlut 0.9 1.1 1.5 ns t gate 0.0 0.0 0.0 ns t casc 0.6 0.7 0.9 ns t cico 0.4 0.5 0.6 ns t cgen 0.4 0.5 0.7 ns t cgenr 0.9 1.1 1.5 ns t c 1.6 2.0 2.5 ns t ch 4.0 4.0 4.0 ns t cl 4.0 4.0 4.0 ns t co 0.4 0.5 0.6 ns t comb 0.4 0.5 0.6 ns t su 0.8 1.1 1.2 ns t h 0.9 1.1 1.5 ns t pre 0.6 0.7 0.8 ns t clr 0.6 0.7 0.8 ns symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t drr 16.0 20.0 25.0 ns t odh 1.0 1.0 1.0 ns
46 altera corporation flex 8000 programmable logic device family data sheet epf81188a internal timing parameters epf81188a i/o element timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t iod 0.7 0.8 0.9 ns t ioc 1.7 1.8 1.9 ns t ioe 1.7 1.8 1.9 ns t ioco 1.0 1.0 1.0 ns t iocomb 0.3 0.2 0.1 ns t iosu 1.4 1.6 1.8 ns t ioh 0.0 0.0 0.0 ns t ioclr 1.2 1.2 1.2 ns t in 1.5 1.6 1.7 ns t od1 1.1 1.4 1.7 ns t od2 1.6 1.9 2.2 ns t od3 4.6 4.9 5.2 ns t xz 1.4 1.6 1.8 ns t zx1 1.4 1.6 1.8 ns t zx2 1.9 2.1 2.3 ns t zx3 4.9 5.1 5.3 ns epf81188a interconnect timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t labcasc 0.3 0.3 0.4 ns t labcarry 0.3 0.3 0.4 ns t local 0.5 0.6 0.8 ns t row 5.0 5.0 5.0 ns t col 3.0 3.0 3.0 ns t din_c 5.0 5.0 5.5 ns t din_d 7.0 7.0 7.5 ns t din_io 5.0 5.0 5.5 ns
altera corporation 47 flex 8000 programmable logic device family data sheet flex 8000 3 epf81188a external timing parameters epf81188a le timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t lut 2.0 2.5 3.2 ns t clut 0.0 0.0 0.0 ns t rlut 0.9 1.1 1.5 ns t gate 0.0 0.0 0.0 ns t casc 0.6 0.7 0.9 ns t cico 0.4 0.5 0.6 ns t cgen 0.4 0.5 0.7 ns t cgenr 0.9 1.1 1.5 ns t c 1.6 2.0 2.5 ns t ch 4.0 4.0 4.0 ns t cl 4.0 4.0 4.0 ns t co 0.4 0.5 0.6 ns t comb 0.4 0.5 0.6 ns t su 0.8 1.1 1.2 ns t h 0.9 1.1 1.5 ns t pre 0.6 0.7 0.8 ns t clr 0.6 0.7 0.8 ns symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t drr 16.0 20.0 25.0 ns t odh 1.0 1.0 1.0 ns
48 altera corporation flex 8000 programmable logic device family data sheet epf81500a internal timing parameters epf81500a i/o element timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t iod 0.7 0.8 0.9 ns t ioc 1.7 1.8 1.9 ns t ioe 1.7 1.8 1.9 ns t ioco 1.0 1.0 1.0 ns t iocomb 0.3 0.2 0.1 ns t iosu 1.4 1.6 1.8 ns t ioh 0.0 0.0 0.0 ns t ioclr 1.2 1.2 1.2 ns t in 1.5 1.6 1.7 ns t od1 1.1 1.4 1.7 ns t od2 1.6 1.9 2.2 ns t od3 4.6 4.9 5.2 ns t xz 1.4 1.6 1.8 ns t zx1 1.4 1.6 1.8 ns t zx2 1.9 2.1 2.3 ns t zx3 4.9 5.1 5.3 ns epf81500a interconnect timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t labcasc 0.3 0.3 0.4 ns t labcarry 0.3 0.3 0.4 ns t local 0.5 0.6 0.8 ns t row 6.2 6.2 6.2 ns t col 3.0 3.0 3.0 ns t din_c 5.0 5.0 5.5 ns t din_d 8.2 8.2 8.7 ns t din_io 5.0 5.0 5.5 ns
altera corporation 49 flex 8000 programmable logic device family data sheet flex 8000 3 epf81500a external timing parameters epf81500a le timing parameters symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t lut 2.0 2.5 3.2 ns t clut 0.0 0.0 0.0 ns t rlut 0.9 1.1 1.5 ns t gate 0.0 0.0 0.0 ns t casc 0.6 0.7 0.9 ns t cico 0.4 0.5 0.6 ns t cgen 0.4 0.5 0.7 ns t cgenr 0.9 1.1 1.5 ns t c 1.6 2.0 2.5 ns t ch 4.0 4.0 4.0 ns t cl 4.0 4.0 4.0 ns t co 0.4 0.5 0.6 ns t comb 0.4 0.5 0.6 ns t su 0.8 1.1 1.2 ns t h 0.9 1.1 1.5 ns t pre 0.6 0.7 0.8 ns t clr 0.6 0.7 0.8 ns symbol a-2 speed grade a-3 speed grade a-4 speed grade unit min max min max min max t drr 16.1 20.1 25.1 ns t odh 1.0 1.0 1.0 ns
50 altera corporation flex 8000 programmable logic device family data sheet power consumption the supply power for flex 8000 devices, p, can be calculated with the following equation: p = p int + p io = [(i cc standby + i cc active ) v cc ] + p io typical i cc standby values are shown as i cc0 in the ?lex 8000 5.0-v device dc operating conditions?table on page 28 and the ?lex 8000 3.3-v device dc operating conditions?table on page 29 . the p io value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in application note 74 (evaluating power for altera devices) . the i cc active value depends on the switching frequency and the application logic. this value can be calculated based on the amount of current that each le typically consumes. the following equation shows the general formula for calculating i cc active : the parameters in this equation are shown below: f max = maximum operating frequency in mhz n = total number of logic cells used in the device tog lc = average percentage of logic cells toggling at each clock k = constant, shown in table 13 this calculation provides an i cc estimate based on typical conditions with no output load. the actual i cc value should be veri?d during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. figure 20 shows the relationship between i cc and operating frequency for several le utilization values. i cc active k f m ax n tog lc m a mhz le --------------------------- - = table 13. values for constant k device k 5.0-v flex 8000 devices 75 3.3-v flex 8000 devices 60
altera corporation 51 flex 8000 programmable logic device family data sheet flex 8000 3 figure 20. flex 8000 i cc active vs. operating frequency con?uration & operation the flex 8000 architecture supports several configuration schemes to load a design into the device(s) on the circuit board. this section summarizes the device operating modes and available device configuration schemes. f for more information, go to application note 33 (configuring flex 8000 devices) and application note 38 (configuring multiple flex 8000 devices) . frequency (mhz) 30 60 100 i cc supply current (ma) 200 les 150 les 100 les 50 les 10 20 30 40 50 60 70 80 90 0 3.3-v flex 8000 devices 5.0-v flex 8000 devices 30 60 0 400 600 1,000 i cc supply current (ma) 800 200 1,000 les 500 les 1,500 les frequency (mhz)
52 altera corporation flex 8000 programmable logic device family data sheet operating modes the flex 8000 architecture uses sram elements that require configuration data to be loaded whenever the device powers up and begins operation. the process of physically loading the sram programming data into the device is called configuration . during initialization, which occurs immediately after configuration, the device resets registers, enables i/o pins, and begins to operate as a logic device. the i/o pins are tri-stated during power-up, and before and during configuration. the configuration and initialization processes together are called command mode ; normal device operation is called user mode . sram elements allow flex 8000 devices to be reconfigured in-circuit with new programming data that is loaded into the device. real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different programming data, reinitializing the device, and resuming user-mode operation. the entire reconfiguration process requires less than 100 ms and can be used to dynamically reconfigure an entire system. in-field upgrades can be performed by distributing new configuration files. con?uration schemes the configuration data for a flex 8000 device can be loaded with one of six configuration schemes, chosen on the basis of the target application. both active and passive schemes are available. in the active configuration schemes, the flex 8000 device functions as the controller, directing the loading operation, controlling external eprom devices, and completing the loading process. the clock source for all active configuration schemes is an oscillator on the flex 8000 device that operates between 2 mhz and 6 mhz. in the passive configuration schemes, an external controller guides the flex 8000 device. table 14 shows the data source for each of the six configuration schemes. table 14. data source for configuration configuration scheme acronym data source active serial as altera configuration eprom active parallel up apu parallel eprom active parallel down apd parallel eprom passive serial ps serial data path passive parallel synchronous pps intelligent host passive parallel asynchronous ppa intelligent host
altera corporation 53 flex 8000 programmable logic device family data sheet flex 8000 3 device pin-outs tables 15 through 17 show the pin names and numbers for the dedicated pins in each flex 8000 device package. table 15. flex 8000 84-, 100-, 144- & 160-pin package pin-outs (part 1 of 3) pin name 84-pin plcc epf8282a 84-pin plcc epf8452a epf8636a 100-pin tqfp epf8282a epf8282av 100-pin tqfp epf8452a 144-pin tqfp EPF8820A 160-pin pga epf8452a 160-pin pqfp EPF8820A note (1) nsp (2) 75 75 75 76 110 r1 1 msel0 (2) 74 74 74 75 109 p2 2 msel1 (2) 53 53 51 51 72 a1 44 nstatus (2) 32 32 24 25 37 c13 82 nconfig (2) 33 33 25 26 38 a15 81 dclk (2) 10 10 100 100 143 p14 125 conf_done (2) 11 11 1 1 144 n13 124 nws 30 30 22 23 33 f13 87 nrs 48 48 42 45 31 c6 89 rdclk 49 49 45 46 12 b5 110 ncs 29 29 21 22 4 d15 118 cs 28 28 19 21 3 e15 121 rdynbusy 77 77 77 78 20 p3 100 clkusr 50 50 47 47 13 c5 107 add17 51 51 49 48 75 b4 40 add16 36 55 28 54 76 e2 39 add15 56 56 55 55 77 d1 38 add14 57 57 57 57 78 e1 37 add13 58 58 58 58 79 f3 36 add12 60 60 59 60 83 f2 32 add11 61 61 60 61 85 f1 30 add10 62 62 61 62 87 g2 28 add9 63 63 62 64 89 g1 26 add8 64 64 64 65 92 h1 22 add7 65 65 65 66 94 h2 20 add6 66 66 66 67 95 j1 18 add5 67 67 67 68 97 j2 16 add4 69 69 68 70 102 k2 11 add3 70 70 69 71 103 k1 10 add2 71 71 71 72 104 k3 8 add1 76 72 76 73 105 m1 7
54 altera corporation flex 8000 programmable logic device family data sheet add0 78 76 78 77 106 n3 6 data7 3 2 90 89 131 p8 140 data6 4 4 91 91 132 p10 139 data5 6 6 92 95 133 r12 138 data4 7 7 95 96 134 r13 136 data3 8 8 97 97 135 p13 135 data2 9 9 99 98 137 r14 133 data1 13 13 4 4 138 n15 132 data0 14 14 5 5 140 k13 129 sdout (3) 79 78 79 79 23 p4 97 tdi (4) 55 45 (5) 54 96 17 tdo (4) 27 27 (5) 18 18 102 tck (4) 72 44 (5) 72 88 27 tms (4) 20 43 (5) 11 86 29 trst (6) 52 52 (7) 50 71 45 dedicated inputs (8) 12, 31, 54, 73 12, 31, 54, 73 3, 23, 53, 73 3, 24, 53, 74 9, 26, 82, 99 c3, d14, n2, r15 14, 33, 94, 113 vccint 17, 38, 59, 80 17, 38, 59, 80 6, 20, 37, 56, 70, 87 9, 32, 49, 59, 82 8, 28, 70, 90, 111 b2, c4, d3, d8, d12, g3, g12, h4, h13, j3, j12, m4, m7, m9, m13, n12 3, 24, 46, 92, 114, 160 vccio 16, 40, 60, 69, 91, 112, 122, 141 23, 47, 57, 69, 79, 104, 127, 137, 149, 159 table 15. flex 8000 84-, 100-, 144- & 160-pin package pin-outs (part 2 of 3) pin name 84-pin plcc epf8282a 84-pin plcc epf8452a epf8636a 100-pin tqfp epf8282a epf8282av 100-pin tqfp epf8452a 144-pin tqfp EPF8820A 160-pin pga epf8452a 160-pin pqfp EPF8820A note (1)
altera corporation 55 flex 8000 programmable logic device family data sheet flex 8000 3 gnd 5, 26, 47, 68 5, 26, 47, 68 2, 13, 30, 44, 52, 63, 80, 94 19, 44, 69, 94 7, 17, 27, 39, 54, 80, 81, 100,101, 128, 142 c12, d4, d7, d9, d13, g4, g13, h3, h12, j4, j13, l1, m3, m8, m12, m15, n4 12, 13, 34, 35, 51, 63, 75, 80, 83, 93, 103, 115, 126, 131, 143, 155 no connect (n.c.) 2, 6, 13, 30, 37, 42, 43, 50, 52, 56, 63, 80, 87, 92, 93, 99 total user i/o pins 64 64 74 64 108 116 116 table 15. flex 8000 84-, 100-, 144- & 160-pin package pin-outs (part 3 of 3) pin name 84-pin plcc epf8282a 84-pin plcc epf8452a epf8636a 100-pin tqfp epf8282a epf8282av 100-pin tqfp epf8452a 144-pin tqfp EPF8820A 160-pin pga epf8452a 160-pin pqfp EPF8820A note (1)
56 altera corporation flex 8000 programmable logic device family data sheet table 16. flex 8000 160-, 192- & 208-pin package pin-outs (part 1 of 2) pin name 160-pin pqfp epf8452a 160-pin pqfp efp8636a 192-pin pga epf8636a EPF8820A 208-pin pqfp epf8636a (1) 208-pin pqfp EPF8820A (1) 208-pin pqfp epf81188a (1) nsp (2) 120 1 r15 207 207 5 msel0 (2) 117 3 t15 4 4 21 msel1 (2) 84 38 t3 49 49 33 nstatus (2) 37 83 b3 108 108 124 nconfig (2) 40 81 c3 103 103 107 dclk (2) 1 120 c15 158 158 154 conf_done (2) 4 118 b15 153 153 138 nws 30 89 c5 114 114 118 nrs 71 50 b5 66 116 121 rdclk 73 48 c11 64 137 137 ncs 29 91 b13 116 145 142 cs 27 93 a16 118 148 144 rdynbusy 125 155 a8 201 127 128 clkusr 76 44 a10 59 134 134 add17 78 43 r5 57 43 46 add16 91 33 u3 43 42 45 add15 92 31 t5 41 41 44 add14 94 29 u4 39 40 39 add13 95 27 r6 37 39 37 add12 96 24 t6 31 35 36 add11 97 23 r7 30 33 31 add10 98 22 t7 29 31 30 add9 99 21 t8 28 29 29 add8 101 20 u9 24 25 26 add7 102 19 u10 23 23 25 add6 103 18 u11 22 21 24 add5 104 17 u12 21 19 18 add4 105 13 r12 14 14 17 add3 106 11 u14 12 13 16 add2 109 9 u15 10 11 10 add1 110 7 r13 8 10 9 add0 123 157 u16 203 9 8 data7 144 137 h17 178 178 177 data6 150 132 g17 172 176 175
altera corporation 57 flex 8000 programmable logic device family data sheet flex 8000 3 data5 152 129 f17 169 174 172 data4 154 127 e17 165 172 170 data3 157 124 g15 162 171 168 data2 159 122 f15 160 167 166 data1 11 115 e16 149 165 163 data0 12 113 c16 147 162 161 sdout (3) 128 152 c7 (9) 198 124 119 tdi (4) 55 r11 72 20 tdo (4) 95 b9 120 129 tck (4) 57u87430 tms (4) 59u77632 trst (6) 40r35454 dedicated inputs (8) 5, 36, 85, 116 6, 35, 87, 116 a5, u5, u13, a13 7, 45, 112, 150 17, 36, 121, 140 13, 41, 116, 146 vccint (5.0 v) 21, 41, 53, 67, 80, 81, 100, 121, 133, 147, 160 4, 5, 26, 85, 106 c8, c9, c10, r8, r9, r10, r14 5, 6, 33, 110, 137 5, 6, 27, 48, 119, 141 4, 20, 35, 48, 50, 102, 114, 131, 147 vccio (5.0 v or 3.3 v) 25, 41, 60, 70, 80, 107, 121, 140, 149, 160 d3, d4, d9, d14, d15, g4, g14, l4, l14, p4, p9, p14 32, 55, 78, 91, 102, 138, 159, 182, 193, 206 26, 55, 69, 87, 102, 131, 159, 173, 191, 206 3, 19, 34, 49, 69, 87, 106, 123, 140, 156, 174, 192 gnd 13, 14, 28, 46, 60, 75, 93, 107, 108, 126, 140, 155 15, 16, 36, 37, 45, 51, 75, 84, 86, 96, 97, 117, 126, 131, 154 c4, d7, d8, d10, d11, h4, h14, k4, k14, p7, p8, p10, p11 19, 20, 46, 47, 60, 67, 96, 109, 111, 124, 125, 151, 164, 171, 200 15, 16, 37, 38, 60, 78, 96, 109, 110, 120, 130, 142, 152, 164, 182, 200 11, 12, 27, 28, 42, 43, 60, 78, 96, 105, 115, 122, 132, 139, 148, 155, 159, 165, 183, 201 no connect (n.c.) 2, 3, 38, 39, 70, 82, 83, 118, 119, 148 2, 39, 82, 119 c6, c12, c13, c14, e3, e15, f3, j3, j4, j14, j15, n3, n15, p3, p15, r4 (10) 1, 2, 3, 16, 17, 18, 25, 26, 27, 34, 35, 36, 50, 51, 52, 53, 104, 105, 106, 107, 121, 122, 123, 130, 131, 132, 139, 140, 141, 154, 155, 156, 157, 208 1, 2, 3, 50, 51, 52, 53, 104, 105, 106, 107, 154, 155, 156, 157, 208 1, 2, 51, 52, 53, 54, 103, 104, 157, 158, 207, 208 total user i/o pins 116 114 132, 148 (11) 132 148 144 table 16. flex 8000 160-, 192- & 208-pin package pin-outs (part 2 of 2) pin name 160-pin pqfp epf8452a 160-pin pqfp efp8636a 192-pin pga epf8636a EPF8820A 208-pin pqfp epf8636a (1) 208-pin pqfp EPF8820A (1) 208-pin pqfp epf81188a (1)
58 altera corporation flex 8000 programmable logic device family data sheet table 17. flex 8000 225-, 232-, 240-, 280- & 304-pin package pin-outs (part 1 of 3) pin name 225-pin bga EPF8820A 232-pin pga epf81188a 240-pin pqfp epf81188a 240-pin pqfp epf81500a 280-pin pga epf81500a 304-pin rqfp epf81500a nsp (2) a15 c14 237 237 w1 304 msel0 (2) b14 g15 21 19 n1 26 msel1 (2) r15 l15 40 38 h3 51 nstatus (2) p2 l3 141 142 g19 178 nconfig (2) r1 r4 117 120 b18 152 dclk (2) b2 c4 184 183 u18 230 conf_done (2) a1 g3 160 161 m16 204 nws l4 p1 133 134 f18 167 nrs k5 n1 137 138 g18 171 rdclk f1 g2 158 159 m17 202 ncs d1 e2 166 167 n16 212 cs c1 e3 169 170 n18 215 rdynbusy j3 k2 146 147 j17 183 clkusr g2 h2 155 156 k19 199 add17 m14 r15 58 56 e3 73 add16 l12 t17 56 54 e2 71 add15 m15 p15 54 52 f4 69 add14 l13 m14 47 45 g1 60 add13 l14 m15 45 43 h2 58 add12 k13 m16 43 41 h1 56 add11 k15 k15 36 34 j3 47 add10 j13 k17 34 32 k3 45 add9 j15 j14 32 30 k4 43 add8 g14 j15 29 27 l1 34 add7 g13 h17 27 25 l2 32 add6 g11 h15 25 23 m1 30 add5 f14 f16 18 16 n2 20 add4 e13 f15 16 14 n3 18 add3 d15 f14 14 12 n4 16 add2 d14 d15 7 5 u1 8 add1 e12 b17 5 3 u2 6 add0 c15 c15 3 1 v1 4 data7 a7 a7 205 199 w13 254 data6 d7 d8 203 197 w14 252 data5 a6 b7 200 196 w15 250 data4 a5 c7 198 194 w16 248
altera corporation 59 flex 8000 programmable logic device family data sheet flex 8000 3 data3 b5 d7 196 193 w17 246 data2 e6 b5 194 190 v16 243 data1 d5 a3 191 189 u16 241 data0 c4 a2 189 187 v17 239 sdout (3) k1 n2 135 136 f19 169 tdi f15 (4) 63 (12) b1 (12) 80 (12) tdo j2 (4) 117 (12) c17 (12) 149 (12) tck j14 (4) 116 (12) a19 (12) 148 (12) tms j12 (4) 64 (12) c2 (12) 81 (12) trst (6) p14 115 a18 145 dedicated inputs (8) f4, l1, k12, e15 c1, c17, r1, r17 10, 51, 130, 171 8, 49, 131, 172 f1, f16, p3, p19 12, 64, 164, 217 vccint (5.0 v) f5, f10, e1, l2, k4, m12, p15, h13, h14, b15, c13 e4, h4, l4, p12, l14, h14, e14, r14, u1 20, 42, 64, 66, 114, 128, 150, 172, 236 18, 40, 60, 62, 91, 114, 129, 151, 173, 209, 236 b17, d3, d15, e8, e10, e12, e14, r7, r9, r11, r13, r14, t14 24, 54, 77, 144, 79, 115, 162, 191, 218, 266, 301 vccio (5.0 v or 3.3 v) h3, h2, p6, r6, p10, n10, r14, n13, h15, h12, d12, a14, b10, a10, b6, c6, a2, c3, m4, r2 n10, m13, m5, k13, k5, h13, h5, f5, e10, e8, n8, f13 19, 41, 65, 81, 99, 116, 140, 162, 186, 202, 220, 235 17, 39, 61, 78, 94, 108, 130, 152, 174, 191, 205, 221, 235 d14, e7, e9, e11, e13, r6, r8, r10, r12, t13, t15 22, 53, 78, 99, 119, 137, 163, 193, 220, 244, 262, 282, 300 gnd b1, d4, e14, f7, f8, f9, f12, g6, g7, g8, g9, g10, h1, h4, h5, h6, h7, h8, h9, h10, h11, j6, j7, j8, j9, j10, k6, k7, k8, k9, k11, l15, n3, p1 a1, d6, e11, e7, e9, g4, g5, g13, g14, j5, j13, k4, k14, l5, l13, n4, n7, n9, n11, n14 8, 9, 30, 31, 52, 53, 72, 90, 108, 115, 129, 139, 151, 161, 173, 185, 187, 193, 211, 229 6, 7, 28, 29, 50, 51, 71, 85, 92, 101, 118, 119, 140, 141, 162, 163, 184, 185, 186, 198, 208, 214, 228 d4, d5, d16, e4, e5, e6, e15, e16, f5, f15, g5, g15, h5, h15, j5, j15, k5, k15, l5, l15, m5, m15, n5, n15, p4, p5, p15, p16, r4, r5, r15, r16, t4, t5, t16, u17 9, 11, 36, 38, 65, 67, 90, 108, 116, 128, 150, 151, 175, 177, 206, 208, 231, 232, 237, 253, 265, 273, 291 table 17. flex 8000 225-, 232-, 240-, 280- & 304-pin package pin-outs (part 2 of 3) pin name 225-pin bga EPF8820A 232-pin pga epf81188a 240-pin pqfp epf81188a 240-pin pqfp epf81500a 280-pin pga epf81500a 304-pin rqfp epf81500a
60 altera corporation flex 8000 programmable logic device family data sheet notes to tables: (1) perform a complete thermal analysis before committing a design to this device package. see application note 74 (evaluating power for altera devices) in this data book for more information. (2) this pin is a dedicated pin and is not available as a user i/o pin. (3) sdout will drive out during configuration. after configuration, it may be used as a user i/o pin. by default, the max+plus ii software will not use sdout as a user i/o pin; the user can override the max+plus ii software and use sdout as a user i/o pin. (4) if the device is not configured to use the jtag bst circuitry, this pin is available as a user i/o pin. (5) jtag pins are available for epf8636a devices only. these pins are dedicated user i/o pins. (6) trst is a dedicated input pin for jtag use. this pin must be grounded if jtag bst is not used. (7) pin 52 is a v cc pin on epf8452a devices only. (8) unused dedicated inputs should be tied to ground on the board. (9) sdout does not exist in the epf8636gc192 device. (10) these pins are no connect (n.c.) pins for epf8636a devices only. they are user i/o pins in EPF8820A devices. (11) epf8636a devices have 132 user i/o pins; EPF8820A devices have 148 user i/o pins. (12) for epf81500a devices, these pins are dedicated jtag pins and are not available as user i/o pins. if jtag bst is not used, trst must be grounded. tms , tdi , and tck should be tied to v cc . revision history the information contained in the flex 8000 programmable logic device family data sheet version 9.11 supersedes information published in previous versions. version 9.11 change the flex 8000 programmable logic device family data sheet version 9.11 contains the following change: figure 14 has been updated for accuracy. no connect (n.c.) 61, 62, 119, 120, 181, 182, 239, 240 10, 21, 23, 25, 35, 37, 39, 40, 41, 42, 52, 55, 66, 68, 146, 147, 161, 173, 174, 176, 187, 188, 189, 190, 192, 194, 195, 205, 207, 219, 221, 233, 234, 235, 236, 302, 303 total user i/o pins 148 180 180 177 204 204 table 17. flex 8000 225-, 232-, 240-, 280- & 304-pin package pin-outs (part 3 of 3) pin name 225-pin bga EPF8820A 232-pin pga epf81188a 240-pin pqfp epf81188a 240-pin pqfp epf81500a 280-pin pga epf81500a 304-pin rqfp epf81500a
altera, max, max+plus, max+plus ii, ahdl, flex, flex 8000, fasttrack interconnect, and specific device designations are trademarks and/or service marks of altera corporation in the united states and other countries. altera products are protected under numerous u.s. and foreign patents and pending applications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera? standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. copyright 1998 altera corporation. all rights reserved. 101 innovation drive s an jose, ca 95134-2020 (408) 544-7000 a pplications hotline: (800) 800-epld c ustomer marketing: (408) 544-7104 literature services: (408) 544-7144 flex 8000 programmable logic device family data sheet 61 altera corporation printed on recycled paper. version 9.10 changes the flex 8000 programmable logic device family data sheet version 9.10 contains the following changes: n updated timing information for a-4 speed grade epf8282av devices. n added timing information for a-3 speed grade epf8282av devices.

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